se m te c h today's results ... tomorrow's vision sk10lve111e SK100LVE111E low voltage 1:9 differential ecl/pecl clock driver with enable input features 200 ps part-to-part skew 50 ps output-to-output skew differential design v bb output enable input voltage and temperature compensated outputs low voltage v ee range of e3,0 to e3.8v 75k w internal pulldown resistors fully compatible with motorola mc100lve111 specified over industrial temperature range: e40?c to 85?c esd protection of >2000v available in 28-pin plcc package description the sk10/1000lve111e is a low skew 1-to-9 differential driver designed with clock distribution in mind. the sk10/ 100lve111e?s function and performance are similar to the sk100e111, with the added feature of low voltage operation. it accepts one signal input which can be either differential or single-ended if the v bb output is used. the signal is fanned out to 9 identical differential outputs. an enable input is also provided. a high disables the device by focing all q outputs low and all q* outputs high. the device is specifically designed, modeled, and produced with low skew as the key goal. optimal design and layout serve to minimize gate-to-gate skew within a device, and characterization is used to determine process control limits that ensure consistent tpd distributions from lot to lot. the net result is a dependable, guaranteed low skew device. to ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50 w , even if only one side is being used. in most applications, all nine differential pairs will be used and therefore terminated. in the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side in order to maintain minimum skew. failure to do this will result in small degradations of propagation delay (on the order of 10e20ps) october 6, 1999 28 pin plcc package preliminary information this document contains information on a new product. the parametric information, although not fully characterized, is the result of testing initial devices. low voltage 1:9 differential ecl / pecl clock driver of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. the sk10/100lve111e, as with most other ecl devices, can be operated from a positive vcc supply in pecl mode. this allows the lve111e to be used for high performance clock distribution in +3.3v systems. designers can take advantage of the lve111e?s performance to distribute low skew clocks across the backplane or the board. in a pecl environment, series or thevenin line terminations are typically used as they require no additional power supplies. for systems incorporating gtl, parallel termination offers the lowest power by taking advantage of the 1.2v supply as a terminating voltage.
se m te c h today's results ... tomorrow's vision sk10lve111e SK100LVE111E low voltage 1:9 differential ecl/pecl clock driver with enable input n i p n o i t c n u f * n i , n i * n e * 0 q , 0 q - * 8 q , 8 q b b v r i a p t u p n i l a i t n e r e f f i d e l b a n e s t u p t u o l a i t n e r e f f i d t u p t u o b b v l o b m y s r e t e m a r a p g n i t a r t i n u v e e ) v 0 = c c v ( y l p p u s r e w o p5 . 4 -0 o tv v i ) v 0 = c c v ( e g a t l o v t u p n io t 04 -0 .v i t u o : t n e r r u c t u p t u o s u o u n i t n o c e g r u s 0 5 0 0 1 a m a m t a e g n a r e r u t a r e p m e t g n i t a r e p o-5 8 + o t 0 4 o c v e e ) 4 e t o n (e g n a r g n i t a r e p o8 . 3 -o t0 . 3 -v t e r o t s e g n a r e r u t a r e p m e t e g a r o t s-0 5 1 + o t 5 6 o c absolute maximum ratings (note 3) q3 q3* q4 vcc0 q4* q5 q5* vee en* in vcc in* vbb n/c q8 q8* q7 vcc0 q7* q6 q6* q0 q0* q1 vcc0 q1* q2 q2* 1 2 3 4 25 24 23 22 21 20 19 567891011 26 27 28 18 17 16 15 14 13 12 28 lead plcc (top view) q0 q0* q1 q1* q2 q2* q3 q3* q4 q4* q5 q5* q6 q6* q7 q7* q8 q8* in in* v bb en*
se m te c h today's results ... tomorrow's vision sk10lve111e SK100LVE111E low voltage 1:9 differential ecl/pecl clock driver with enable input l o b m y s c i t s i r e t c a r a h c n i m p y t x a m n i m p y t x a m n i m p y t x a m n i m p y t x a m t i n u v h o e g a t l o v h g i h t u p t u o-5 3 1 10 9 8 -0 8 0 1 -0 4 8 -0 2 0 1 -0 1 8 -0 1 9 -0 2 7 -v m v l o e g a t l o v w o l t u p t u o0 5 9 1 -0 5 6 1 -0 5 9 1 -0 3 6 1 -0 5 9 1 -0 3 6 1 -0 5 9 1 -5 9 5 1 -v m v h i e g a t l o v h g i h t u p n i0 3 2 1 -0 9 8 -0 7 1 1 -0 4 8 -0 3 1 1 -0 1 8 -0 6 0 1 -0 2 7 -v m v l i e g a t l o v w o l t u p n i0 5 9 1 -0 0 5 1 -0 5 9 1 -0 8 4 1 -0 5 9 1 -0 8 4 1 -0 5 9 1 -5 4 4 1 -v m v b b e g a t l o v e c n e r e f e r t u p t u o-3 4 . 10 3 . 1 -8 3 . 1 -7 2 . 1 -5 3 . 1 -5 2 . 1 -1 3 . 1 -9 1 . 1 -v i h i t n e r r u c h g i h t u p n i0 5 10 5 10 5 10 5 1a i l i t n e r r u c w o l t u p n i5 . 05 . 05 . 03 . 0a i e e t n e r r u c y l p p u s r e w o p5 35 65 35 65 35 65 35 6a m sk10lve111e ecl dc electrical characteristics ta = e40?c ta = 0?c ta = +25?c ta = +85?c sk10lve111e pecl dc electrical characteristics l o b m y s c i t s i r e t c a r a h c n i m p y t x a m n i m p y t x a m n i m p y t x a m n i m p y t x a m t i n u v h o e g a t l o v h g i h t u p t u o 7 5 6 1 20 1 2 30 2 2 20 2 4 20 8 2 20 9 4 20 9 3 20 8 5 2v m v l o e g a t l o v w o l t u p t u o 7 0 5 3 10 5 6 10 5 3 10 7 6 10 5 3 10 7 6 10 5 3 15 0 7 1v m v h i e g a t l o v h g i h t u p n i 7 0 7 0 20 1 4 20 3 1 20 6 4 20 7 1 20 1 4 20 4 2 20 8 5 2v m v l i e g a t l o v w o l t u p n i 7 0 5 3 10 0 8 10 5 3 10 2 8 10 5 3 10 2 8 10 5 3 15 5 8 1v m v b b e g a t l o v e c n e r e f e r t u p t u o 7 7 8 . 10 0 . 22 9 . 13 0 . 25 9 . 15 0 . 29 9 . 11 1 . 2v i h i t n e r r u c h g i h t u p n i0 5 10 5 10 5 10 5 1v i l i t n e r r u c w o l t u p n i5 . 05 . 05 . 03 . 0a i e e t n e r r u c y l p p u s r e w o p6 66 66 66 6a m ta = e40?c ta = 0?c ta = +25?c ta = +85?c (v ee = v ee (min) to v ee (max); v cc = gnd) (notes 1 and 4) (v cc = v cc (min) to v cc (max); v ee = gnd) (notes 1 and 4)
se m te c h today's results ... tomorrow's vision sk10lve111e SK100LVE111E low voltage 1:9 differential ecl/pecl clock driver with enable input l o b m y s c i t s i r e t c a r a h c n i m p y t x a m n i m p y t x a m n i m p y t x a m n i m p y t x a m t i n u v h o e g a t l o v h g i h t u p t u o-4 1 . 15 0 0 . 1 --0 8 8 . 0-8 0 . 1-5 5 9 . 0-0 8 8 . 08 0 . 1 --5 5 9 . 0-0 8 8 . 08 0 . 1 --5 5 9 . 0-0 8 8 . 0v v l o e g a t l o v w o l t u p t u o-3 8 . 1-5 9 6 . 1-5 5 5 . 1-0 1 8 . 1-5 0 7 . 1-0 2 6 . 1-0 1 8 . 1-5 0 7 . 1-0 2 6 . 1-0 1 8 . 1-5 0 7 . 1-0 2 6 . 1v v h i e g a t l o v h g i h t u p n i-5 6 1 . 1-0 8 8 . 0-5 6 1 . 1-0 8 8 . 0-5 6 1 . 1-0 8 8 . 0-5 6 1 . 1-0 8 8 . 0v v l i e g a t l o v w o l t u p n i-0 1 8 . 1-5 7 4 . 1-0 1 8 . 1-5 7 4 . 1-0 1 8 . 1-5 7 4 . 1-0 1 8 . 1-5 7 4 . 1v v b b e g a t l o v e c n e r e f e r t u p t u o-8 3 . 1-6 2 . 1-8 3 . 1-6 2 . 1-8 3 . 1-6 2 . 1-8 3 . 1-6 2 . 1v v e e e g a t l o v y l p p u s r e w o p-0 . 3-8 . 3-0 . 3-8 . 3-0 . 3-8 . 3-0 . 3-8 . 3v i h i t n e r r u c h g i h t u p n i0 5 10 5 10 5 10 5 1a i e e t n e r r u c y l p p u s r e w o p5 56 65 56 65 56 65 68 7a m SK100LVE111E ecl dc electrical characteristics ta = e40?c ta = 0?c ta = +25?c ta = +85?c SK100LVE111E pecl dc electrical characteristics l o b m y s c i t s i r e t c a r a h c n i m p y t x a m n i m p y t x a m n i m p y t x a m n i m p y t x a m t i n u v h o e g a t l o v h g i h t u p t u o 7 6 1 . 25 9 2 . 20 2 4 . 22 2 . 25 4 3 . 20 2 4 . 22 2 . 25 4 3 . 20 2 4 . 22 2 . 25 4 3 . 20 2 4 . 2v v l o e g a t l o v w o l t u p t u o 7 0 7 4 . 10 1 6 . 10 5 7 . 10 9 4 . 15 9 5 . 10 8 6 . 10 9 4 . 15 9 5 . 10 8 6 . 10 9 4 . 15 9 5 . 10 8 6 . 1v v h i e g a t l o v h g i h t u p n i 7 5 3 1 . 20 2 4 . 25 3 1 . 20 2 4 . 25 3 1 . 20 2 4 . 25 3 1 . 20 2 4 . 2v v l i e g a t l o v w o l t u p n i 7 0 9 4 . 15 2 8 . 10 9 4 . 15 2 8 . 10 9 4 . 15 2 8 . 10 9 4 . 15 2 8 . 1v v b b e g a t l o v e c n e r e f e r t u p t u o 7 2 9 . 14 0 . 22 9 . 14 0 . 22 9 . 14 0 . 22 9 . 14 0 . 2v v c c e g a t l o v y l p p u s r e w o p0 . 38 . 30 . 38 . 30 . 38 . 30 . 38 . 3v i h i t n e r r u c h g i h t u p n i0 5 10 5 10 5 10 5 1a i e e t n e r r u c y l p p u s r e w o p5 56 65 56 65 56 65 68 7a m ta = e40?c ta = 0?c ta = +25?c ta = +85?c (v ee = v ee (min) to v ee (max); v cc = gnd) (notes 2 and 4) (v cc = v cc (min) to v cc (max); v ee = gnd) (notes 2 and 4)
se m te c h today's results ... tomorrow's vision sk10lve111e SK100LVE111E low voltage 1:9 differential ecl/pecl clock driver with enable input ac characteristics (v ee = v ee (min) to v ee (max); v cc = v cco = gnd) (note 4) -0 4 o c 0 o c 5 2 o c 5 8 o c l o b m y s c i t s i r e t c a r a h c n i m p y t x a m n i m p y t x a m n i m p y t x a m n i m p y t x a m t i n u d n o c t h l p t l h p o t y a l e d n o i t a g a p o r p t u p t u o ) l a i t n e r e f f i d ( n i ) d e d n e - e l g n i s ( n i 0 0 4 0 5 3 0 5 6 0 0 7 5 3 4 5 8 3 5 2 6 5 7 6 0 4 4 0 9 3 0 3 6 0 8 6 5 4 4 5 9 3 5 3 6 5 8 6 s p . 8 . 9 t w e k s w e k s e c i v e d - n i h t i w ) f f i d ( w e k s t r a p - o t - t r a p 0 5 0 5 2 0 5 0 5 2 0 5 0 5 2 0 5 0 5 2 s p . 0 1 v p p g n i w s t u p n i m u m i n i m0 0 50 0 50 0 50 0 5v m. 1 1 v r m c e g n a r e d o m n o m m o c-5 . 1-4 . 0-5 . 1-4 . 0-5 . 1-4 . 0-5 . 1-4 . 0v . 2 1 t r t , f e m i t l l a f / e s i r % 0 8 o t % 0 2 0 0 20 0 60 0 20 0 60 0 20 0 60 0 20 0 6s p% 0 2-% 0 8 notes: 1. 10lve111e circuits are designed to meet the dc specifications shown in the table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintaine d. outputs are termionated through a 50 w resistor to e2.0v. 2. the same dc parameter values apply across the full vee range of e3.0 to e3.8v. outputs are terminated through a 50 w resistor to e2.0v. 100lve111e circuits are designed to meet the dc specifications shown in the table where transverse airflow greater than 500 lfpm is maintained. 3. absolute maximum rating, beyond which device life may be impaired unless otherwise specificed on an individual data sheet. 4. parametric values specified at: 10lve111e series: e3.0 to e3.8v 100 lve111e series: e3.0 to e3.8v; pecl power supply: +3.0v to +3.8v 5. guaranteed high signal for all inputs. 6. guaranteed low signal for all inputs. 7. these values are for vcc = 3.3v. level specifications will vary 1:1 with vcc. 8. the differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 9. the single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of theoutp ut signal. 10. the within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 11. v pp (min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. the v pp (min) is ac limited for the e111 as a differential input as low as 50 mv will still produce full ecl levels at the output. 12. v cmr is defined as the range within which the v ih level may vary, with the device still meeting the propagation delay specification. the v il level must be such that the peak-to-peak voltage is less than 1.0v and greater than or equal to v pp (min).
se m te c h today's results ... tomorrow's vision sk10lve111e SK100LVE111E low voltage 1:9 differential ecl/pecl clock driver with enable input package information ? ? ? 28 1 v w y brk d d + + z x u b g1 0.007 (0.180) t l ?m n m s s 0.007 (0.180) t l ?m n m s s 0.010 (0.250) t l ?m n s s s k k1 h f 0.007 (0.180) t l ?m n m s s 0.007 (0.180) t l ?m n m s s m i d n i m x a m n i m x a m a5 8 4 . 05 9 4 . 02 3 . 2 17 5 . 2 1 b5 8 4 . 05 9 4 . 02 3 . 2 17 5 . 2 1 c5 6 1 . 00 8 1 . 00 2 . 47 5 . 4 e0 9 0 . 00 1 1 . 09 2 . 29 7 . 2 f3 1 0 . 09 1 0 . 03 3 . 08 4 . 0 g0 5 0 . 0c s b7 2 . 1c s b h6 2 0 . 02 3 0 . 06 6 . 01 8 . 0 j0 2 0 . 0- -1 5 . 0- - k5 2 0 . 0- -4 6 . 0- - r0 5 4 . 06 5 4 . 03 4 . 1 18 5 . 1 1 u0 5 4 . 06 5 4 . 03 4 . 1 18 5 . 1 1 v2 4 0 . 08 4 0 . 07 0 . 11 2 . 1 w2 4 0 . 08 4 0 . 07 0 . 11 2 . 1 x2 4 0 . 06 5 0 . 07 0 . 12 4 . 1 y- -0 2 0 . 0- -0 5 . 0 z2 o 0 1 o 2 o 0 1 o 1 g0 1 4 . 00 3 4 . 02 4 . 0 12 9 . 0 1 1 k0 4 0 . 0- -2 0 . 1- - millimeters inches + + z 0.007 (0.180) t l ?m n m s s 0.007 (0.180) t l ?m n m s s j 0.010 (0.250) t l ?m n s s s a r e c g1 g 0.004 (0.100) ? seating plane view s view s view d-d notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dim g1, true position to be measured at datum -t-, seating plane. 3. dim r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch betweeen the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635).
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